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description the LCX005BK is a 1.4cm diagonal active matrix tft-lcd panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. this panel provides full-color representation in ntsc/pal mode. rgb dots are arranged in a delta pattern featuring high picture quality of no fixed color patterns, which is inherent in vertical stripes and mosaic pattern arrangements. features the number of active dots: 113,578 (0.55-inch; 1.397cm in diagonal) horizontal resolution: 260 tv lines high optical transmittance: 3.4% (typ.) high contrast ratio with normally white mode: 270 (typ.) built-in h and v drivers (built-in input level conversion circuit, ttl drive possible) high quality picture representation with rgb delta arranged color filters full-color representation ntsc/pal compatible right/left inverse display function element structure dots total dots : 537 (h) 222 (v) = 119,214 active dots: 521 (h) 218 (v) = 113,578 built-in peripheral driver using polycrystalline silicon super thin film transistors. applications viewfinders super compact liquid crystal monitors etc. ?1 LCX005BK e94z24a5x-ps 1.4cm (0.55-inch) ntsc/pal color lcd panel sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
?2 LCX005BK block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 h shift register v shift register c s lc com pad v dd v ss vst vck2 vck1 en clr rgt hst hck2 hck1 (nc) blue red green com h level conversion circuit v level conversion circuit
?3 LCX005BK absolute maximum ratings (v ss = 0v) h and v driver supply voltages v dd ?.0 to +17 v h driver input pin voltage hst, hck1, hck2 ?.0 to +17 v rgt v driver input pin voltage vst, vck1, vck2 ?.0 to +17 v clr, en video signal input pin voltage green, red, blue ?.0 to +15 v operating temperature topr ?0 to +70 ? storage temperature tstg ?0 to +85 ? operating conditions (v ss = 0v) supply voltage v dd 13.5 0.5 v input pulse voltage (vp-p of all input pins except video signal input pins) vin 2.8v (more than) pin description pin no. 1 2 3 4 (5) 6 7 8 com green red blue (nc) hck1 hck2 hst common voltage of panel video signal (g) to panel video signal (r) to panel video signal (b) to panel not connected clock pulse for h shift register drive clock pulse for h shift register drive start pulse for h shift register drive 9 10 11 12 13 14 15 16 rgt clr en vck1 vck2 vst vss v dd drive direction pulse for h shift register (h: normal, l: reverse) improvement pulse for uniformity enable pulse for gate selection clock pulse for v shift register drive clock pulse for v shift register drive start pulse for v shift register drive gnd (h, v drivers) power supply for h and v drivers symbol description pin no. symbol description
?4 LCX005BK input equivalent circuit to prevent static charges, protective diodes are provided for each pin except the power supply. in addition, protective resistors are added to all pins except video signal input. all pins are connected to vss with a high resistance of 1m (typ.). the equivalent circuit of each input pin is shown below: (the resistor value: typ.) input 1m w lc level conversion circuit (single- phase input) 250 w 250 w v dd input v dd 250 w 250 w 250 w 250 w level conversion circuit (2-phase input) hck1 hck2 input v dd from h driver signal line (1) video signal input (2) hck1, hck2 (3) hst 2.5k w 2.5k w v dd input (5) rgt, vst, clr, en v dd 2.5k w 2.5k w 1k w 1k w vck1 vck2 (4) vck1, vck2 (6) com 1m w 1m w 1m w 1m w 1m w 1m w 1m w level conversion circuit (single- phase input) level conversion circuit (2-phase input)
?5 LCX005BK level conversion circuit the LCX005BK has a built-in level conversion circuit in the clock input unit located inside the panel. the circuit voltage is stepped up to v dd inside the panel. this level conversion circuit meets the specifications of a 3.0v to 5.0v power supply of the externally-driven ic. 1. i/o characteristics of level conversion circuit (for a single-phase input unit) an example of the i/o voltage characteristics of a level conversion circuit is shown in the figure to the right. the input voltage value that becomes half the output voltage (after voltage conversion) is defined as vth. the vth value varies depending on the v dd voltage. the vth values under standard conditions are indicated in the table below. (hst, vst, en, clr, and rgt in the case of a single-phase input) v dd = 13.5v v dd 2 v dd vth input voltage [v] example of single-phase i/o characteristics output voltage (inside panel) item vth voltage of circuit vth 0.4 1.50 2.75 v symbol min. typ. max. unit (for a differential input unit) an example of i/o voltage characteristics of a level conversion circuit for a differential input is shown in the figure to the right. although the characteristics, including those of the vth voltage, are basically the same as those for a single-phased input, the two- phased input phase is defined. (refer to clock timing conditions.) v dd 2 v dd vth input voltage [v] example of differential i/o characteristics output voltage (inside panel) 2. current characteristics at the input pin of level conversion circuit a slight pull-in current is generated at the input pin of the level conversion circuit. (the equivalent circuit is shown to the right.) the current volume increases as the voltage at the input pin decreases, and is maximized when the pin is grounded. (refer to electrical characteristics.) v dd output hck1 input hck2 input level conversion equivalent circuit 0 0 max. value input pin voltage [v] 10 pull-in current characteristics at the input pin input pin current
?6 LCX005BK input signals 1. input signal voltage conditions (v ss = 0v) item h driver input voltage (hst, hck1, hck2, rgt) (low) (high) (low) (high) vhil vhih vvil vvih vvc vsig vcom ?.35 2.8 ?.35 2.8 5.8 vvc ?4.5 vvc ?0.55 0.0 5.0 0.0 5.0 6.0 vvc ?0.40 +0.35 5.5 +0.35 5.5 6.2 vvc + 4.5 vvc ?0.25 v v v v v v v v driver input voltage (vst, vck1, vck2, clr, en) video signal center voltage video signal input range * 1 common voltage of panel symbol min. typ. max. unit * 1 video input signal shall be symmetrical to vvc. 2. clock timing conditions (ta = 25?, input voltage = 5.0v) hst rise time hst fall time hst data set-up time hst data hold time hckn * 2 rise time hckn * 2 fall time hck1 fall to hck2 rise time hck1 rise to hck2 fall time clr rise time clr fall time clr pulse width clr fall to hst rise time vst rise time vst fall time vst data set-up time vst data hold time vckn * 2 rise time vckn * 2 fall time vck1 fall to vck2 rise time vck1 rise to vck2 fall time en rise time en fall time vck2 rise to en fall time vck1 rise to en rise time trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck trclr tfclr twclr tohst trvst tfvst tdvst thvst trvckn tfvckn to1vck to2vck tren tfen tdvck2 tdvck1 ?70 ?55 ?5 ?5 3400 1100 ?0 ?0 ?00 ?00 ?00 ?00 135 ?35 0 0 3500 1200 32 ?2 0 0 0 0 100 100 170 ?0 100 100 15 15 100 100 3600 1300 100 100 50 ?0 100 100 100 100 100 100 100 100 ns ? ns item symbol min. typ. max. unit hst hck clr vst vck en * 2 hckn and vckn mean hck1, hck2 and vck1, vck2. (fhckn = 1.84mhz, fvckn = 7.865khz)
?7 LCX005BK hst rise time hst hck clr hst fall time hst data set-up time hst data hold time hckn * 2 rise time hckn * 2 fall time hck1 fall to hck2 rise time hck1 rise to hck2 fall time clr rise time clr fall time clr pulse width clr fall to hst rise time hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns tdhst = 135ns thhst = ?35ns tdhst = 135ns thhst = ?35ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck trclr tfclr twclr tohst item symbol waveform conditions 90% 10% 10% 90% hst trhst tfhst 50% 50% * 3 hst hck1 tdhst thhst 50% 50% * 2 hckn 10% 10% 90% 90% trhckn tfhckn 50% 50% * 3 hck1 to2hck to1hck 50% 50% hck2 clr 90% 90% 10% 10% trclr tfclr clr 50% 50% 50% twclr tohst hst
?8 LCX005BK * 3 definitions: the right-pointing arrow ( ) means +. the left-pointing arrow ( ) means ? the black dot at an arrow ( ) indicates the start of measurement. vst rise time vst vck en vst fall time vst data set-up time vst data hold time vckn * 2 rise time vckn * 2 fall time vck1 fall to vck2 rise time vck1 rise to vck2 fall time en rise time en fall time vck1 rise to en rise time vck2 rise to en fall time vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns tdvst = 32s thvst = ?2s tdvst = 32s thvst = ?2s vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns trvst tfvst tdvst thvst trvckn tfvckn to1vck to2vck tren tfen tdvck1 tdvck2 item symbol waveform conditions 90% 10% 10% 90% vst trvst tfvst 50% 50% * 3 vst vck1 tdvst thvst 50% 50% vckn 10% 10% 90% 90% trvckn tfvckn 50% 50% * 3 vck1 to2vck to1vck 50% 50% vck2 90% 90% 10% 10% tfen tren 50% * 3 vck1 tdvck2 tdvck1 50% 50% en en 50%
?9 LCX005BK electrical characteristics 1. horizontal drivers (ta = 25?, v dd = 13.5v, input voltage = 5.0v) item input pin capacitance hckn hst input pin current hck1 hck2 hst rgt video signal input pin capacitance chckn chst ihck1 ihck2 ihst irgt csig hck1 = gnd hck2 = gnd hst = gnd rgt = gnd ?00 ?00 ?00 ?00 5 5 ?0 ?60 ?00 ?5 30 10 10 45 pf pf ? ? ? ? pf symbol min. typ. max. unit condition 2. vertical drivers item input pin capacitance vckn vst input pin current vck1 vck2 vst en clr cvckn cvst ivck1 ivck2 ivst ien iclr ?00 ?00 ?00 5 5 ?0 ?00 ?5 10 10 pf pf ? ? ? symbol min. typ. max. unit condition 3. total power consumption of the panel item total power consumption of the panel (ntsc) pwr 35 55 mw symbol min. typ. max. unit 4. vcom input resistance item vcom ?vss input resistance rcom 0.5 1 m symbol min. typ. max. unit vck1 = gnd vck2 = gnd vst, en, clr = gnd
?10 LCX005BK electro-optical characteristics (ta = 25?, ntsc mode) item contrast ratio 25? 60? x y x y x y 25? 60? 25? 60? 25? 60? r vs. g b vs. g 0? 25? 0? 25? 60? 60 min. cr 25 cr 60 t rx ry gx gy bx by v 90-25 v 90-60 v 50-25 v 50-60 v 10-25 v 10-60 v 50rg v 50bg ton0 ton25 toff0 toff25 f yt60 80 80 2.6 0.560 0.300 0.275 0.541 0.120 0.040 1.1 1.0 1.5 1.4 2.2 2.1 270 270 3.4 0.630 0.345 0.310 0.595 0.148 0.088 1.6 1.5 2.0 1.8 2.5 2.4 ?.10 0.10 30 8 65 20 0.670 0.390 0.347 0.650 0.187 0.122 2.2 2.1 2.5 2.4 3.2 3.1 ?.25 0.45 100 40 150 60 ?0 20 1 2 3 4 5 6 7 8 % cie standards v v ms db s optical transmittance chromaticity r g b v 90 v 50 v 10 on time off time v-t characteristics half tone color reproduction range response time flicker image retention time symbol measurement method min typ. max. unit
?11 LCX005BK

* measurement system i lcd panel luminance meter measurement equipment back light: color temperature 6500k, +0.004uv (25?) * back light spectrum (reference) is listed on another page. optical fiber lcd panel light receptor lens drive circuit light source basic measurement conditions (1) driving voltage v dd = 13.5v vvc = 6.0v, vcom = 5.6v (2) measurement temperature 25? unless otherwise specified. (3) measurement point one point in the center of screen unless otherwise specified. (4) measurement systems two types of measurement system are used as shown below. (5) rgb input signal voltage (vsig) vsig = 6 v ac (v) (v ac : signal amplitude) back light 3.5mm * measurement system ii measurement equipment light detector 1. contrast ratio contrast ratio (cr) is given by the following formula (1). cr = ...(1) l (white): surface luminance of the tft-lcd panel at the rgb signal amplitude v ac = 0.5v. l (black): surface luminance of the panel at v ac = 4.5v. both luminosities are measured by system i . l (white) l (black)
?12 LCX005BK 2. optical transmittance optical transmittance (t) is given by the following formula (2). t = 100 [%] ...(2) l (white) is the same expression as defined in the "contrast ratio" section. 3. chromaticity chromaticity of the panels are measured by system i . raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. system i uses chromaticity of x and y on the cie standards here. signal amplitudes (v ac ) supplied to each input r input g input b input raster r g b 0.5 4.5 4.5 4.5 0.5 4.5 4.5 4.5 0.5 (unit : v) 4. v-t characteristics v-t characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by system ii . v 90 , v 50 and v 10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. (transmittance at v ac = 0.5v is 100%.) 5. half tone color reproduction range half tone color reproduction range of the lcd panels is characterized by the differences between the v-t characteristics of r, g and b. the differences of these v-t characteristics are measured by system ii . system ii defines signal voltages of each r, g, b raster modes which correspond to 50% of transmittance, v 50r , v 50g and v 50b respectively. v 50rg and v 50bg , the voltage differences between v 50r and v 50g , v 50b and v 50g , are simply given by the following formulas (3) and (4) respectively. v 50rg = v 50r ?v 50g ...(3) v 50bg = v 50b ?v 50g ...(4) 90 50 10 v 90 v 50 v 10 v ac ?signal amplitude [v] transmittance [%] 100 50 0 v 50r v 50b v 50g v ac ?signal amplitude [v] transmittance [%] v 50rg v 50bg g raster b raster r raster l (white) luminance of back light
?13 LCX005BK 6. response time response time ton and toff are defined by the formulas (5) and (6) respectively. ton = t1 ?ton ...(5) toff = t2 ?toff ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. the relationships between t1, t2, ton and toff are shown in the right figure. 7. flicker flicker (f) is given by the formula (7). dc and ac (ntsc: 30hz, rms, pal: 25hz, rms) components of the panel output signal for gray raster * mode are measured by a dc voltmeter and a spectrum analyzer in system ii . f (db) = 20log {} ...(7) 8. image retention time apply the monoscope signal to the lcd panel for 60 minutes and then change this signal to the gray scale of vsig = 6 v ac (v ac : 3 to 4v), judging by sight at v ac that hold the maximum image retention, measure the time till the residual image becomes indistinct. * monoscope signal conditions: vsig = 6 4.5 or 6 2.0 (v) (shown in the right figure) v com = 5.6v input signal voltage (waveform applied to the measured pixels) 4.5v 0.5v 6v 0v optical transmittance output waveform 100% 90% 10% 0% ton t1 ton toff t2 toff * r, g, b input signal condition for gray raster mode is given by vsig = 6 v 50 (v) where: v 50 is the signal amplitude which gives 50% of transmittance in v-t characteristics. black level white level vsig waveform 6v 0v 4.5v 2.0v 4.5v 2.0v ac component dc component
?14 LCX005BK example of back light spectrum (reference) 0.4 0.3 0.2 0.1 0 400 500 600 700 wavelength 380 ?780 [nm]
?15 LCX005BK description of operation 1. color coding color filters are coded in a delta arrangement. the shaded area is used for the dark border around the display. b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r r b g r b g r b g r b g r b g r g gate sw gate sw gate sw gate sw 537 3 521 13 2 2 218 222 gate sw gate sw green is not connected for only final stage. photo-shielding g b g b g b g b g b active area
?16 LCX005BK 2. lcd panel operations a vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 218 gate lines sequentially in every horizontal scanning period. a vertical shift register scans the gate lines from the top to bottom of the panel. the selected pulse is delivered when the enable pin turns to high level. pal mode images are displayed by controlling the enable and vck1, vck2 pins. the enable pin should be high when not in use. a horizontal driver, which consists of horizontal shift registers, gates and cmos sample-and-hold circuits applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period. scanning direction of horizontal shift register can be switched with rgt pin. scanning direction is left to right for rgt pin at high level; and right to left for rgt pin at low level. (these scanning directions are from a front view.) normally, set to high level. vertical and horizontal drivers address one pixel and then turn on thin film transistors (tfts; two tfts) to apply a video signal to the dot. the same procedures lead to the entire 218 521 dots to display a picture in a single vertical scanning period. pixel dots are arranged in a delta pattern, where sets of rgb pixels are positioned with 1.5-dot shifted against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal synchronized signal is required to apply a video signal to each dot properly. 1h reversed displaying mode is required to apply video signal to the panel. the clr pin is provided to eliminate the shading effect caused by the coupling of selected pulses. while maintaining the clr at high level, the v dd potential of gate output inverter drops to approximately 8.5v. this pin shall be grounded when not in use. the video signal shall be input with polarity-inverted system in every horizontal cycle. timing diagrams of the vertical and the horizontal right-direction scanning (rgt = high level) display cycle are shown below: vertical display cycle 218h (13.84ms) 1 2 218 217 (1) vertical display cycle vd vst vck1 vck2 horizontal display cycle (47.3s) 123 45 175 174 (2) horizontal display cycle (right scan) blk hst hck1 hck2 * hst is sampled at first for hck1. the horizontal display cycle consists of 521/3 = 174 clock pulses because of rgb simultaneous sampling. * refer to description of operation "3. rgb simultaneous sampling." * vst is sampled at first for vck2.
?17 LCX005BK 3. rgb simultaneous sampling horizontal driver samples r, g and b signal simultaneously, which requires the phase matching between r, g and b signals to prevent horizontal resolution from deteriorating. thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the lcd panel. two methods are applied for the delaying procedure: sample and hold and delay circuit. these two block diagrams are as follows. the LCX005BK has the right/left inverse function. the following phase relationship diagram indicates the phase setting for the right scan (rgt = high level). for the left scan (rgt = low level), the phase setting shall be inverted between b and g signals. (1) sample and hold (right scan) (right scan) s/h s/h ac amp s/h ac amp s/h ac amp s/h (2) delay circuit (right scan) delay delay ac amp delay ac amp ac amp 4 3 b r g blue red green ckb ckr ckg ckg ckg hckn ckb ckr ckg blue red green b r g LCX005BK LCX005BK 2 4 3 2
?18 LCX005BK example of color filter spectrum (reference) 400 500 600 700 wavelength [nm] transmittance [%] 0 20 40 60 80 100 b g r color filter spectrum
?19 LCX005BK color display system block diagram (1) an example of single-chip display system is shown below. y/color difference y/c lcd panel ntsc/pal LCX005BK cxa1854r red green blue hck1 hst vst hck2 vck1 en vck2 clr rgt (refer to cxd1845r data sheet.) composite video +12v +5v +13.5v vcom
?20 LCX005BK color display system block diagram (2) an example of dual-chip display system is shown below. y/color difference y/c lcd panel ntsc/pal LCX005BK decoder/driver cxa1785ar tg cxd2411r red green blue hck1 hst vst hck2 vck1 en vck2 clr rgt (refer to cxd2411r data sheet.) +5v frp sync composite video +12v +5v +13.5v vcom
?21 LCX005BK notes on handling (1) static charge prevention be sure to take following protective measures. tft-lcd panels are easily damaged by static charge. a) use non-chargeable gloves, or simply use bare hands. b) use an earth-band when handling. c) do not touch any electrodes of a panel. d) wear non-chargeable clothes and conductive shoes. e) install conductive mat on the working floor and working table. f) keep panels away from any charged materials. g) use ionized air to discharge the panels. (2) protection from dust and dirt a) operate in clean environment. b) when delivered, a surface of a panel (polarizer) is covered by a protective sheet. peel off the protective sheet carefully not to damage the panel. c) do not touch the surface of a panel. the surface is easily scratched. when cleaning, use a clean-room wiper with isopropyl alcohol. be careful not to leave stain on the surface. d) use ionized air to blow off dust at a panel. (3) other handling precautions a) do not twist or bend the flexible pc board especially at the connecting region because the board is easily deformed. b) do not drop a panel. c) do not twist or bend a panel or a panel frame. d) keep a panel away from heat source. e) do not dampen a panel with water or other solvents. f) avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages.
?22 LCX005BK package outline unit: mm pin 1 pin 16 0.5 0.1 p 0.5 0.02 15 = 7.5 0.03 0.5 0.15 3.0 0.3 4.0 0.5 18.0 0.15 9.0 0.25 (11.2) 2.7 0.15 (8.3) 7.7 0.25 17.8 0.15 25.5 0.8 34.8 0.8 1.2 0.3 thickness of the connector 0.3 0.05 14.0 0.3 8.5 0.05 4-r1.0 0.35 + 0.04 ?0.03 s-c k1 description molding material outside frame reinforcing board reinforcing material polarizing film f p c no 1 2 3 4 5 6 weight 1.3g electrode (enlarged) active area active area incident light 1 2 3 4 5 6 6

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